92706 / 22706 ms ot b8-4910 no.a0224-1/10 LA75501V overview the LA75501V is an adjustment free vif/sif signal processing ic for pal tv/vcr. it supports 38mhz, 38.9mhz, and 39.5mhz as the if frequencies, as well as pal sound multi- system (m/n,b/g, i, d/k), and contains an on-chip sound carrier trap and sound carrier bpf. to adjust the vco circu it, aft circuit, and sound filte r, 4mhz external crystal or 4mhz external signal is needed. function ? vif block: vif amplifier, pll detector, if agc, rf agc, equalizer, amplifier, buzz canceller, sif trap, digital aft, fll, 4mhz x?tal oscillation ? 1st sif block: 1st sif amplifier, 1st sif detector, 1st sif agc ? sif block: limiter amplifier down converter, pll fm detector sif pll sif vco, sif bpf ? others: if sw (38.9mhz, 38mhz), sif4 syst em sw (b/g, i, d/k, m/n), ifagc 2nd filter specifications maximum ratings at ta = 25 c parameter symbol conditions ratings unit maximum supply voltage v cc 7v v 16 v cc v circuit voltage v 18 v cc v i 30 -1 ma i 17 +0.5 ma i 6 -10 ma circuit current i 4 -3 ma allowable power dissipation pd max ta 80 c * 500 mw operating temperature topr -20 to +85 c storage temperature tstg -55 to +150 c * mounted on a board : 65 72 1.6mm 3 ,paper phenol board. ordering number : ena0224 monolithic linear ic for use in tv/vtr applications vif/sif signal processing ic any and all sanyo semiconductor products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. consult with your sanyo semiconductor representative nearest you before using any sanyo semiconductor products described or contained herein in such applications. sanyo semiconductor assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo semiconductor products described or contained herein. www.datasheet.co.kr datasheet pdf - http://www..net/
LA75501V no.a0224-2/10 operating ranges at ta = 25 c parameter symbol conditions ratings unit recommended supply voltage v cc 5.0 v operating supply voltage v cc op 4.5 to 6.0 v electrical characteristics at ta = 25c, v cc = 5v, fp = 38.9mhz vif block ratings parameter symbol conditions min typ max unit circuit current i 21 64.0 73.6 ma maximum rf agc voltage v 17 h 8.5 9 v minimum rf agc voltage v 17 l collector load 30k vc2 = 9v 0.0 0.3 0.7 v input sensitivity vi 33 39 45 db v agc range gr 58 db maximum allowable input vi max 92 97 db v no-signal video output voltage v 6 2.9 3.3 3.7 v sync. signal tip voltage v 6 tip 0.9 1.2 1.5 v video output amplitude v o 1.5 1.8 2.1 vp-p video s/n s/n b/g 48 52 db c-s best ic-s ps = 10db 26 32 38 db differential gain dg 80db , 87.5% mod 5 10 % differential phase dp 80db , 87.5% mod 2 10 c black noise threshold voltage v bth 0.7 v black noise clamp voltage v bcl 1.8 v vif input resistance r i 2.5 3.0 k ? vif input capacitance c i 3 6 pf maximum aft voltage v 16 h 4.3 4.7 5.0 v minimum aft voltage v 16 l 0 0.2 0.7 v aft tolerance 1 dfa1 f = 38.9mhz 35 70 khz aft tolerance 2 dfa2 f = 38.0mhz 35 70 khz atf detection sensitivity sf r l = 100k//100k ? 30 55 80 mv/khz aft dead zone fda 30 60 mhz apc pull-in range (u) fpu 1.5 2.0 mhz apc pull-in range (l) fpl 1.5 2.0 mhz vco maximum variable range (u) dfu 1.5 2.0 mhz vco maximum variable range (l) dfl 1.5 2.0 mhz vco control sensitivity 2.0 4.0 8.0 khz/mv n trap 1 (4.5m) nt1 -30 -35 db n trap 2 (4.8m) nt1-1 -19 -24 db b/g trap 1 (5.5m) bt1 -27 -32 db b/g trap 2 (5.85m) bt1-1 -20 -25 db i trap 1 (6.0m) it1 -25 -30 db i trap 2 (6.55m) it1-1 -15 -20 db d/k trap1 (6.5m) dt1 -25 -30 db group delay 1 ntsc (3.0m) ngd1 30 60 90 ns group delay 1-1 ntsc (3.5m) ngd1-1 160 230 300 ns group delay 2 b/g (4m) bgd2 70 100 130 ns group delay 2-1 b/g (4.4m) bgd2-1 160 230 300 ns group delay 3 i (4m) bgd3 20 50 80 ns group delay 3-1 i (4.4m) bgd3-1 60 90 120 ns group delay 4 d/k (4m) bgd4 0 30 60 ns group delay 4-1 d/k (4.4m) bgd4-1 10 40 70 ns www.datasheet.co.kr datasheet pdf - http://www..net/
LA75501V no.a0224-3/10 1st sif block ratings parameter symbol conditions min typ max unit conversion gain v g fp-5.5mhz,vi = 500 v 26 32 36 db sif carrier output level so vi = 10mv 100 mvrms 1st sif maximum input si max so 2db 106 db v 1st sif input resistance r i s 2.0 2.4 k ? 1st sif input capacitance c i s 3 6 pf sif block ratings parameter symbol conditions min typ max unit limiting sensitivity vi (lim) 46 52 58 db v fm detector output voltage v o (fm) f = 5.5mhz ? f = 30khz at 400hz 480 600 750 mvrms am rejection ratio amr am = 30% at 400hz 50 60 db distortion thd f = 5.5mhz ? f = 30khz 0.3 1.0 % fm detector output s/n s/n (fm) din. audio 55 60 db bpf 3db band width bw 100 khz pal de-emphasis pdeem fm = 3khz -3 db ntsc de-emphasis ndeem fm = 2khz -3 db pal/nt audio voltage gain difference gd 6 db others ratings parameter symbol conditions min typ max unit minimum 4mhz level (at external input) x 4 min terminal value 80 86 92 db sif system sw threshold voltage v 13 v 14 1.4 v if system sw threshold voltage v 15 270 k ? split/inter sw v 20 0.5 v system changeover sw/sif system sw the sif system can be changed over by setting a (pin 13) and b (pin 14) to gnd and the open state respectively. a b b/g i d/k m/n fm det level de-emphasis gnd gnd o 6db 75 s gnd open o 0db 50 s open gnd o 0db 50 s open open o 0db 50 s note: ?o? indicates that the system is selected. if system sw the if frequency is selected 38.9mhz mode with the pin 15 (crystal oscillation) open. the if frequency is selected 38mhz mode by adding 220k ? between the pin 15 and gnd. inter carrier sw inter-carrier is selected by setting the 1st sif input (pin 20) to gnd. www.datasheet.co.kr datasheet pdf - http://www..net/
LA75501V no.a0224-4/10 package dimensions unit : mm 3191b pin assignment 9.75 5.6 7.6 0.22 0.65 (0.33) 1 15 16 30 0.5 0.15 1.5max 0.1 (1.3) sanyo : ssop30(275mil) www.datasheet.co.kr datasheet pdf - http://www..net/
LA75501V no.a0224-5/10 block diagram and ac charac teristics test circuit input impedance test circuit la75510v www.datasheet.co.kr datasheet pdf - http://www..net/
LA75501V no.a0224-6/10 test conditions v1. circuit current [i 21 ] (1) external agc (v 18 = 1.5v) (2) rf agc vr max (3) connect an ammeter to the v cc and measure the incoming current to pin 17. v2. v3. maximum rf agc voltage, minimum rf agc voltage [v 17 h, v 17 l] (1) internal agc (2) input a 38.9mhz, 10mvrms, continuous wave to the vif input pin. (3) adjust the rf agc vr (resistance max. ) and measure the maximum rf agc voltage. (4) adjust the rf agc vr (resistance min. ) and measure the minimum rf agc voltage. (3), (4) measuring point f v4. input sensitivity [vi] (1) internal agc (2) fp = 38.9mhz 400hz 40% am (vif input) (3) turn off the sw1 and put 100k ? through. (4) measure the vif input level at which the 400hz detection output level at test point a becomes 0.7vp-p. v5. agc range [gr] (1) apply the v cc voltage to the external agc, if agc (pin 18). (2) in the same manner under the same conditions as for v4 (input sensitivity), measure the vif input level at which the detection output level becomes 0.7vp-p. vil *vi: input sensitivity (3) gr = 20log db v6. maximum allowable input [vi max] (1) internal agc (2) fp = 38.9mhz 15khz 78% am (vif input) (3) vif input level at which the detection output level at test point a becomes video output (v o ) 1db. v7. no-signal video output voltage [v 6 ] (1) apply the v cc voltage to the external agc, if agc (pin 18). (2) measure the dc voltage of video output (a). v8. sync. signal tip voltage [v 6 tip] (1) internal agc (2) input a 38.9mhz, 10mvrms, continuous wave to the vif input pin. (3) measure the dc voltage of video output (a). v9. video output level [v o ] (1) internal agc (2) fp = 38.9mhz 15khz 78% am vi = 10mvrms (vif input) (3) measure the peak value of the detection output level at test point a. (vp-p) v10. video s/n [s/n] (1) internal agc (2) fp = 38.9mhz cw = 10mvrms (vif input) (3) measure the noise voltage at test point a in rms volts through a 10khz to 4mhz band-pass filter. noise voltage (n) (4) s/n = 20log = 20log (db) vil vi video voltage (vp-p) n (vrms) 1.12vp-p n(vrms) www.datasheet.co.kr datasheet pdf - http://www..net/
LA75501V no.a0224-7/10 v11. c/s beat [ics] (1) apply dc voltage to the external agc if agc (pin 18) and vary it. (2) fp = 38.9mhz cw;10mvrms fc = 34.47mhz cw;10mvrms ? 10db fs = 33.4mhz cw;10mvrms ? 10db (3) adjust the if agc (pin 18) voltage so that the output level at test point a becomes 1.3vp-p. (4) measure the difference between the levels for 4.43mhz and 1.07mhz components at test point a. v12.v13. differential gain, differential phase [dg, dp] (1) internal agc (2) fp = 38.9mhz apl50% 87.5% modulation video signal vi = 10mvrms (3) measure the dg and dp at test point a. v14.v15. black noise threshold and clamp voltage [v bth , v bcl ] (1) apply dc voltage (1 to 3v) to the external agc, if agc (pin 18) and adjust the voltage. (2) fp = 38.9mhz 400hz 40% am 10mvrms (vif input) (3) adjust the if agc (pin 18) voltage to operate the noise canceller. measure the v bth , v bcl at test point a. v16. v17. vif input resist ance, input capacitance [r i , c i ] (1) external agc (v 18 = 2v) (2) referring to the input impedance test circuit, measure r i and c i with an impedance analyzer. www.datasheet.co.kr datasheet pdf - http://www..net/
LA75501V no.a0224-8/10 v18. v19. maximum, minimum aft vo ltage, aft detection sensitivity [v 16 h, v 16 l] (1) internal agc (2) fp = 38.9mhz 1.5mhz vi = 10mvrms (vif input) (3) measure maximum and minimum aft output voltage (at the measuring point b) by changing the input frequency. (4) maximum voltage: v 16 h, minimum voltage: v 16 l. v20.v21.v22.v23. aft tolerance 1,2,aft detector sensitivity, aft dead zone [dfa, sf, fda] (1) measure the frequency deviation when the voltage at the measuring point b changes from v1 to v2. ? f sf (mv/khz) = (2) measure the width in which the voltage at the measuring point b does not change. (3) calculate as follows: fda (khz) = f2 ? f1 (4) calculate as follows: if center frequency: 38.9mhz, 38mhz dfa (khz) = fc ? v24.v25. apc pull-in range [fpu, fpl] (1) internal agc (2) fll: free (3) fp = 33mhz to 44mhz cw;10mvrms (4) adjust the sg signal frequency to be higher than fp = 38.9mhz to bring the pll to unlocked state. note; the pll is taken as in unlocked state when a beat signal appears at test point a. (5) when the sg signal frequency is lowered, the pll is brought to locked state again. f1 (6) lower the sg signal frequency to bring the pll to unlock state. (7) when the sg signal frequency is raised, the pll is brought to locked state again. f2 (8) calculate as follows: fpu = f1 ? 38.9mhz fpl = f2 ? 38.9mhz v26.v27. vco maximum variable range (u, l) [dfu, dfl] (1) apply the v cc voltage to the external agc, if agc (pin 18). (2) fl is taken as the frequency when 1v is app lied to the apc pin (pin 9). in the same manner, fu is taken as the frequency when 5v is applied to the apc pin (pin 9). dpu = fu ? 38.9mhz dfl = fl ? 38.9mhz v1 ? v2 ? f f1 + f2 2 www.datasheet.co.kr datasheet pdf - http://www..net/
LA75501V no.a0224-9/10 v28. vco control sensitivity [ ] (1) apply the v cc voltage to the external agc, if agc (pin 18). (2) apply the 3v to the external fll, fll (pin 10). (3) pick up the vco oscillation frequency from the video output (a), gnd, etc. and adjust the vco coil so that the frequency becomes 38.9mhz. (4) f1 is taken as the frequency when 2.8v is applied to the apc pin (pin 9). in the same manner, f2 is taken as the frequency when 3.2v is applied to the apc pin (pin 9). = f2 ? (khz/mv) f1. 1st sif conversion gain [v g ] (1) internal agc (2) fp = 38.9mhz cw;10mv (vif input) fs = 33.4mhz cw;500 v (1st sif input) v1 (3) measure the detection output level at test point c (5.5mhz) v2 (4) v g = 20log db f2. 5.5mhz output level [so] (1) internal agc (2) fp = 38.9mhz cw; 10mv (vif input) fs = 33.4mhz cw; 10mv (1st sif input) v1 (3) measure the detection output level at test point c (5.5mhz). so (mvrms) f3. 1st maximum input [si max] (1) internal agc (2) fp = 38.9mhz cw; 10mv (vif input) fs = 33.4mhz cw; variable (1st sif input) (3) input level at which the detection output (5.5 mhz) at test point c b ecomes so 2db. si max f4.f5. 1st sif input resistance, input capacitance [r i (sif1), c i (sif1)] (1) referring to the input impedance test circuit, measure r i and c i with an impedance analyzer. s1. sif limiting sensitivity [v i (lim)] (1) apply the v cc voltage to the external agc, if agc (pin 18). (2) fs = 5.5mhz fm = 400hz ? f = 300khz (sif input) (3) set the sif input level to 31.6mvrms and measure the level at test point d. v1 (4) lower the sif input level and measure the input level which becomes v1. 3db. s2.s4. fm detection output voltage, total harmonics distortion [v o (fm), thd] (1) apply the v cc voltage to the external agc, if agc (pin 18). (2) fs = 5.5mhz fm = 400hz ? f = 30khz (sif input vi = 31.6mvrms) (3) measure the fm detection output voltage, total harmonics distortion at test point d. s3. am rejection ratio [amr] (1) external agc (v 18 =v cc ) (2) fs = 5.5mhz fm = 400hz am = 30% (sif input vi = 31.6mvrms) (3) measure the output level at test point d. vam (4) amr = 20log db s5. sif s/n [s/n (fm)] (1) external agc (v 15 = v cc ) (2) fs = 5.5mhz no mod vi = 31.6mvrms (3) measure the output leve l at test point d. vn (4) s/n = 20log db v2 v1 f1 ? f2 400 v o (det) vam v o (det) vn www.datasheet.co.kr datasheet pdf - http://www..net/
LA75501V ps no.a0224-10/10 s7.s8. pal, nt de-emphasis [pdeem, ndeem] (1) external agc (v 18 = v cc ) (2) fs = 5.5mhz fm = 3khz ? f = 30khz (sif input vi = 31.6mvrms) (3) open system switches (a (pin 13) and b (pin 14)). (bg mode) (4) measure the fm det ector output voltage at test point d. vp (5) calculate as follows: pdeem (db) = vp ? v o (fm) (6) fs = 4.5mhz fm = 2khz ? f = 30khz (sif input vi = 31.6mvrms) (7) set system switches [a (pin 13) and b (pin 14)] to gnd. (nt mode) (8) measure the fm det ector output voltage at test point d. vp (9) calculate as follows: ndeem (db) = vnt ? v o (fm) s9. pal/nt audio voltage gain difference [gd] (1) external agc (v 18 =v cc ) (2) fs = 4.5mhz fm = 400hz ? f = 30khz (sif input vi = 31.6mvrms) (3) set system switches [a (pin 13) and b (pin 14)] to gnd. (4) measure the fm det ector output voltage at test point d. vnt (5) calculate as follows: gd (db) = vnt ? v o (fm) specifications of any and all sanyo semiconductor products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. sanyo semiconductor co., ltd. strives to supply high-quality high-reliability products. however, any and all semiconductor products fail with some probability. it is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. in the event that any or all sanyo semiconductor products (including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of sanyo semiconductor co., ltd. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equipment, refer to the "delivery specification" for the sanyo semiconductor product that you intend to use. information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. sanyo semiconductor believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. this catalog provides information as of february, 2006. specifications and information herein are subject to change without notice. www.datasheet.co.kr datasheet pdf - http://www..net/
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